Mechanical stresses within a semiconductor device substrate can modulate device performance. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the NFETs and/or PFETs. But, it is well known that stress components affect the behaviors of NFET and PFET devices differently.
In order to maximize the performance of both NFETs and PFETs within integrated circuit (IC) chips, the stress components should be engineered and applied differently for NFETs and PFETs. The stress components should be engineered and applied differently because the type of stress which is beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET. More particularly, when a device is in tension, the performance characteristics of the NFET is enhanced while the performance characteristics of the PFET is diminished.
To accommodate the different stress requirements, it is known to use different material combinations to apply tensile stress to NFETs and compressive stress to PFETs. In known processes for implementing stresses in FETs, distinct processes and/or materials are used to create the tensile or compressive stresses in the NFETs and PFETs, respectively. It is known, for example, to use a trench isolation structure for the NFET and PFET devices. According to this method, the isolation region for the NFET device contains a first isolation material which applies a first type of mechanical stress on the NFET device in a longitudinal direction and in a transverse direction. Further, a first isolation region and a second isolation region are provided for the PFET and each of the isolation regions of the PFET device applies a unique mechanical stress on the PFET device in the transverse direction.
Additional methods to provide strain for both NFET and PFET include the use of patterned, tensile or compressively strained silicon nitride layers for spacers or gate sidewalls, or for contact studs etch stop liners.
While these methods do provide structures that have tensile stresses being applied to the NFET device and compressive stresses being applied along the longitudinal direction of the PFET device, they require additional materials and/or more complex processing, and thus, result in higher cost. Also, the levels of induced stress with these methods tend to saturate and also become lower with technology scaling. Further, in current fabrication devices, a method and device including both NFET and PFET devices on the same substrate including an embedded SiGe layer in the gate region of the NFET, and an embedded SiGe layer in the PFET source/drain region are provided during separate processes. These more recent methods provide strained channel NFET and PFET devices where the stresses increase with further gate length scaling and are minimally impacted by overall design ground rules scaling.
A drawback in the area of strain for these channels is the formation of misfit dislocations that result in a decrease of charge mobility and thus device performance. Such undesired dislocation misfits form as the device is built and treated at elevated temperature.
The issue of strain relaxation in the silicon film becomes even more critical for thermally mixed silicon germanium on insulator devices (SGOI), where the total film thickness has to be maintained very thin (less than 500 Å). In thermally mixed SGOI a defect-free, relaxed SiGe layer is formed on insulator followed by epitaxial growth of a buffer SiGe layer and then the Si layer. If the final film thickness has to be less than 500 Å, a buffer SiGe layer cannot be grown due to thickness limitations and the strained Si layer has to be grown directly on the thermally mixed SGOI film. In this case the epi growth interface is at the SiGe/Si interface. This interface usually has defects and misfits dislocation generation which result in a strain relaxation during device processing.